• Core architecture: 128 macrocells, 2,500 usable gates
• I/O capability: 84 user I/O pins, 68 programmable I/O
• High speed: Pin-to-pin delay 5ns (maximum), internal counter maximum frequency 192.3MHz
• In system programmable mode: Supports 5.0-V ISP, and enables online programming via the IEEE Std. 1149.1 JTAG interface.
• Storage technology: EEPROM process, non-volatile, starts working immediately upon power-on
• Operating voltage: 3.0V to 3.6V, typical value 3.3V
• JTAG boundary scan: Built-in boundary scan test (BST) circuit, supporting online testing
• Package type: 100-TQFP (Thin Quad Flat Package), 20mm × 20mm, pin pitch 0.5mm
• Operating temperature: Commercial grade temperature range: 0°C to +70°C
• MSL level: Level 1 (unrestricted, unlimited workshop lifespan), low humidity sensitivity level
• Environmental compliance: Meets RoHS standards, lead-free (with "N" suffix)